Many data transmission systems send and receive framed serial data. Each frame of data is identified with a frame pulse that separates it from the preceding frame of data. This frame boundary may be used for alignment of the data being transmitted. For example, when a stream of bits is being transmitted in a multi-channel arrangement, where each channel has ten bits, the first bit represents bit 1 of channel 1, the second bit represents bit 2 of channel 1 . . . the 10th bit represents bit 10 of channel 1 and the 11th bit represents bit 1 of channel 2. The first bit of each channel is a frame pulse and bits 2 to 10 are typically comprised of data bits, however some schemes may provide for bit 2 of each respective channel to be used for verification such as parity. A receiver receiving the serial stream of bits uses the frame pulses for aligning the data bits with their respective channels. Thus frame pulses are used to demark the boundary of clusters of data and provide the receiver with a frame of reference.
The transmission of framed data is shown in a prior art elastic storage circuit for use in a telephone switching system described in U S. Pat. bearing the No. 4,323,790 in the name of Stephen C. Dunning et al. This circuit employs a means of detecting first-in first-out (FIFO) memory overflow or underflow due to a chronic increase or decrease in the frequency rate of the data. The FIFO temporarily stores the data portion of a serial stream having been framed by frame pulses. This circuit does not provide a means of monitoring data corruption.
Data is said to be correctly framed when the number of clock cycles between pairs of successive frame pulses is equal to a predetermined number. However, it is not uncommon for corrupt data to be received at a node of a transmission system; the cause of the data corruption may be unstable clock sources, noise in the system, poor connections, or a myriad of other causes. Often, it is found that extra clock cycles or too few clock cycles occur between two successive frame pulses in a system where the train of frame pulses should be periodic and thus have a predetermined number of clock cycles between each pair thereof. If this situation goes undetected a large amount of corrupt data may be accepted by the receiver before an error control mechanism is able to detect the problem and initiate corrective action. Most of the known data receivers use an input stage that includes an elastic buffer usually in the form of a FIFO. Presently available commercial FIFOs commonly provide fifo-full and fifo-empty indications to denote overflow and underflow conditions as well as read and write pointers. However it is not possible to use the read and write pointers to monitor the contents of the FIFO since they are internal to the devices.
It is thus an object of the invention to provide a novel circuit and method for accepting correctly framed data by detecting if the number of clock cycles between two successive frame pulses is equal to a predetermined number, and accepting the data if the number of clock cycles is equal to the predetermined number.